vcs

vcs(IP_LIB **kwargs)

Create a target for invoking VCS (compilation, elaboration, and simulation) on IP_LIB.

It will create a target run_<IP_LIB>_vcs that will compile, elaborate, and simulate the IP_LIB design.

Parameters

Name	Type	Description
IP_LIB	string	The target IP library, it needs to have SOURCES property set with a list of SystemVerilog or VHDL files.

Keyword Arguments

Name	Type	Description
NO_RUN_TARGET	bool	Do not create a run target.
GUI	bool	Run simulation in GUI mode.
32BIT	bool	Use 32 bit compilation and simulation.
OUTDIR	string	Output directory for the VCS compilation and simulation.
EXECUTABLE_NAME	string	Replace the default name of the generated executable target.
RUN_TARGET_NAME	string	Replace the default name of the run target.
TOP_MODULE	string	Top module name to be used for elaboration and simulation.
LIBRARY	string	replace the default library name (worklib) to be used for elaboration and simulation.
SV_COMPILE_ARGS	string	Extra arguments to be passed to the SystemVerilog / Verilog compilation step.
VHDL_COMPILE_ARGS	string	Extra arguments to be passed to the VHDL compilation step.
ELABORATE_ARGS	string	Extra arguments to be passed to the elaboration step.
RUN_ARGS	string	Extra arguments to be passed to the simulation step.
FILE_SETS	list[string]	Specify list of File sets to retrieve the sources from

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vcs_gen_sc_wrapper(IP_LIB **kwargs)

This function create a target to generate a SystemC wrapper for the IP library, with VCS vlogan, if SystemVerilog or Verilog files are in the IP library.

Parameters

Name	Type	Description
IP_LIB	string	The target IP library, it needs to have SOURCES property set with a list of SystemVerilog or Verilog files.

Keyword Arguments

Name	Type	Description
32BIT	bool	Use 32 bit compilation and simulation.
OUTDIR	string	Output directory for the VCS compilation and simulation.
LIBRARY	string	replace the default library name (worklib) to be used for elaboration and simulation.
TOP_MODULE	string	Top module name to be used for elaboration and simulation.
SV_COMPILE_ARGS	string	Extra arguments to be passed to the SystemVerilog / Verilog compilation step.
VHDL_COMPILE_ARGS	string	Extra arguments to be passed to the VHDL compilation step.
FILE_SETS	list[string]	Specify list of File sets to retrieve the sources from

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vcs_gen_hdl_wrapper(SC_LIB **kwargs)

This function create a target to generate a Verilog wrapper file from a SystemC library with with VCS syscan.

Parameters

Name	Type	Description
SC_LIB	target	Name of an existing CMake target representing the SystemC library.

Keyword Arguments

Name	Type	Description
32BIT	bool	Use 32 bit compilation and simulation.
OUTDIR	string	Output directory for the VCS compilation and simulation.
LIBRARY	string	replace the default library name (worklib) to be used for elaboration and simulation.
TOP_MODULE	string	Top module name to be used for elaboration and simulation.

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vcs_configure_cxx(**kwargs)

.. note:: This is a macro, and so does not introduce a new scope.

This macro is used to configure the C and CXX compiler to the one used by the tool.

It can also be used to add some libraries, such as SystemC and DPI-C in this case, for example if you want to use dpi, you should use this macro like this :

vcs_configure_cxx(LIBRARIES DPI-C)

Keyword Arguments

Name	Type	Description
LIBRARIES	list[string]	Libraries that needs to be added.

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vcs_add_cxx_libs(**kwargs)

This function is called by the vcs_configure_cxx macro, you shouldn't use it directly.

It will add the needed information to IP_LIB and add some flags for the compilation and linking.

Keyword Arguments

Name	Type	Description
32BIT	bool	Use 32 bitness.
LIBRARIES	list[string]	libraries that needs to be added, possible choice are SystemC and/or DPI-C