fpga

vivado(IP_LIB **kwargs)

Generate a vivado FPGA project and create a target to generate the bitstream.

The python script, edalize_vivado, using edalize library is used to correctly run vivado with the given informations. The different arguments are parsed and formatted to be properly given to vivado.

Parameters

Name	Type	Description
IP_LIB	string	The target IP library.

Keyword Arguments

Name	Type	Description
TOP	string	Top-level module name used for elaboration. The default is the IP_LIB IP_NAME property.
VERILOG_DEFINES	list[string]	Additional SV/Verilog define flags to be passed to the Vivado project.
OUTDIR	string	Output directory for generated files. Defaults to ${BINARY_DIR}/vivado.