cmake.utils/generate_sources_list/generate_sv_sources_list
generate_sv_sources_list(IP_LIB **kwargs)
Generate a dependency-ordered Verilog/SystemVerilog source list for an IP target, including only instantiated modules.
This function collects all Verilog/SystemVerilog source files associated with the given IP_LIB target.
It produces two files containing:
- A dependency-ordered list of all Verilog/SystemVerilog source files (rtl_sources.f)
- A list of all include files (include_sources.f)
The hierarchy is parsed using slang (https://github.com/MikePopoloski/slang), ensuring that only the necessary
files for the specified top module (if provided) and its dependencies are included.
Parameters
| Name | Type | Description |
|---|---|---|
IP_LIB | string | Name of the IP library target to analyze. |
Keyword Arguments
| Name | Type | Description |
|---|---|---|
OUTDIR | string | (Optional) Output directory for the generated file lists. Defaults to ${CMAKE_BINARY_DIR}/ip_sources |
TOP_MODULE | string | (Optional) Name of the top module to use as the root of the hierarchy. Only modules below this point are included. An error is reported if the specified module does not exist. |
SLANG_ARGS | list | (Optional) Extra arguments to pass directly to slang. |
FILE_SETS | list | (Optional) Restrict the collected sources and include directories to the listed file sets; all file sets are used when omitted. |