xcelium

xcelium.include_guard(GLOBAL)

Warning

This is a generic command invocation. It is not a function or macro definition.

Create a target for invoking Xcelium (compilation, elaboration, and simulation) on IP_LIB.

It will create a target run_<IP_LIB>_xcelium that will compile, elaborate, and simulate the IP_LIB design.

Parameters:

IP_LIB (INTERFACE_LIBRARY) – RTL interface library, it needs to have SOURCES property set with a list of System Verilog files.

Keyword Arguments

Parameters:

  • NO_RUN_TARGET (bool) – Do not create a run target.

  • GUI (bool) – Run simulation in GUI mode.

  • 32BIT (bool) – Use 32 bit compilation and simulation.

  • OUTDIR (string) – Output directory for the Xcelium compilation and simulation.

  • RUN_TARGET_NAME (string) – Replace the default name of the run target.

  • TOP_MODULE (string) – Top module name to be used for elaboration and simulation.

  • LIBRARY (string) – replace the default library name (worklib) to be used for elaboration and simulation.

  • COMPILE_ARGS (string) – Extra arguments to be passed to the compilation step (C, C++).

  • SV_COMPILE_ARGS (string) – Extra arguments to be passed to the System Verilog / Verilog compilation step.

  • VHDL_COMPILE_ARGS (string) – Extra arguments to be passed to the VHDL compilation step.

  • ELABORATE_ARGS (string) – Extra arguments to be passed to the elaboration step.

  • RUN_ARGS (string) – Extra arguments to be passed to the simulation step.

xcelium.xcelium(IP_LIB **kwargs)
xcelium.__xcelium_compile_lib(IP_LIB **kwargs)
xcelium.__get_xcelium_search_lib_args(IP_LIB **kwargs)
xcelium.__find_xcelium_home(OUTVAR)
xcelium.xcelium_gen_sc_wrapper(IP_LIB **kwargs)
xcelium.xcelium_gen_hdl_wrapper(SC_LIB **kwargs)
xcelium.xcelium_configure_cxx(**kwargs)

Note

This is a macro, and so does not introduce a new scope.

xcelium.xcelium_add_cxx_libs(**kwargs)